Senior DFT Engineer

Senior DFT Engineer Experience : 4–5 years Location : Bangalore Experience to join our Silicon Engineering team. In this role, you will lead end-to-end DFT strategies—including Scan compression, MBIST, IJTAG, and ATPG pattern generation—for high-performance, sub-10nm SoCs. Candidates must have expertise in top-tier EDA tools (Tessent, Synopsys, or Cadence) and a notice period of 0–30 days . Ready to elevate your career? Send your resume to janagaradha.n@acldigital.com today!