AI Accelerator Chip Architect

Roles & Responsibilities Lead architecture and technical strategy for AI/ML acceleration silicon, including compute engines, memory architecture, interconnects, and software enablement. Key Responsibilities: Define AI accelerator architecture.Analyze AI workloads and mapping strategies. Drive NPU/Matrix Engine/MAC architecture decisions. Define memory hierarchy and bandwidth requirements. Guide RTL and verification teams. Support customer technical workshops and solution definition. Drive accelerator roadmap and differentiation. Our Ideal Candidate 15+ years in ASIC/SoC design. Prior experience on AI, GPU, DSP, NPU, TPU, or HPC silicon. Strong understanding of AI workloads and inference pipelines. Experience in compute architecture and memory systems e.g. ARM Neoverse, RISC-V mesh based compute sub-system Compute Sub-system experience Complex NoC experience e.g. Arteris / ARM Understanding on other processor such as ARM A, M and R series Understanding of RTL design and verification. Performance modeling experience and assessment using virtual or emulation platform. Strong customer-facing capability.