Senior DV Engineers (UVM/Verliog)

LTTS is looking for DV engineers with 7 years of experience for lead roledetailed JD is below mentioned. 8/10 of hands-on experience in StemVerilog/UVM methodology and/or C/C++ based verification 8/ 10 experience in IP/sub-stem and/or SoC level verification based on StemVerilog UVM/OVM based methodologies Experience in development of UVM based verification environments from scratch Experience in architecting and implementing Design Verification infrastructure and executing the full verification…