Texas Instruments
Design Verification Engineer
Dallas, TX, United States
Company's own boardBachelor's degree1+ yrs
Posted 2 months ago · First seen Oct 24 · seen live today · from Texas Instruments's own Oracle Cloud board
Skills mentioned
pythonmachine learning
The posting, as published
Change the world. Love your job.
Texas Instruments is seeking a Design Verification Engineer to join our Analog Power Products organization in Dallas. In this role, you will develop and execute verification strategies that ensure first-pass silicon success for next-generation analog and mixed-signal ICs across industrial, automotive, and consumer applications.
As a Design Verification Engineer, you will work across the full verification cycle – from understanding the system/design intent, developing detailed verification plans and building test benches, running regressions, tracking bug closure, and contributing to continuous improvements in DV methodology – collaborating closely with analog design, digital design and systems engineering teams.
Responsibilities include:
Develop detailed verification plans while working closely with the design and system team to ensure first-pass silicon success
Develop test benches, tests, and simulations using Analog and mixed-signal (AMS) skills
Work with regression tools and develop scripts to submit cases for regression analysis
Analyze simulation results to ensure compliance with intended block-level behavior and system interactions
Track and communicate verification status, issues, and concerns
Contribute to continuous improvements for quality and efficiency on DV strategy, tools, methods, and flows
Minimum requirements:
Bachelor’s degree in Electrical Engineering, Electrical and Computer Engineering, or related field
1+ years of experience in AMS design verification or a related role
Preferred qualifications:
Master’s degree in electrical engineering or related field
Strong analog/digital behavior debug skills
Experience with functional verification methodologies including simulation, assertions, and coverage-driven verification
Proficiency in SystemVerilog
Proficiency in Real Number models in SystemVerilog EEnet for analog block abstraction
Familiarity with RTL simulation tools (Cadence Xcelium or equivalent)
Experience in AI/Machine learning for accelerated DV
Scripting skills for regression automation and verification flow development (Python, Tcl, or Perl)
Ability to establish strong relationships with key stakeholders critical to success, both internally and externally
Strong verbal and written communication skills
Demonstrated strong interpersonal, analytical, and problem-solving skills
Ability to work in teams and collaborate effectively with people in different functions
Ability to take the initiative and drive for results